EBMC is a Model Checker for hardware designs. It includes both bounded and unbounded analysis, i.e., it can both discover bugs and is also able to prove the absence of bugs. It can read Netlists (ISCAS89 format), Verilog, System Verilog and SMV files. Properties can be given in LTL or a fragment of System Verilog Assertions.
The unwound circuits can be exported as DIMACS CNF (bit-level) or in the SMT-LIB 1 or 2 format (word-level).
- Bounded Model Checking (BMC)
- Supports fragment of System Verilog assertions for property specification
Versions up to (including) 4.1 have also supported the following methods:
- Completeness threshold computation with structural analysis
- Cut-point abstraction with counterexample-guided refinement
- Model Checking using bit-level interpolation for approximate image computation
- Model Checking using word-level interpolation for approximate image computation
Authors: Daniel Kroening and Mitra Purandare.
NEW: There is now a Google Group for annoucements related to EBMC.
EBMC 4.2 released on 29.8.2015!
The EBMC Manual describes the command line options of EBMC. We also provide papers that provide background on how EBMC works:
- Hardware Verification using Software Analyzers
- Approximation Refinement for Interpolation-Based Model Checking
- Computational Challenges in Bounded Model Checking
- Computing Over-Approximations with Bounded Model Checking
- Efficient Computation of Recurrence Diameters
You should also read the license.
We currently only distribute binaries for x86 Linux and Windows. We do not distribute source code.
- AIG_SMV_08.tar.gz (bit-level SMV files)
EBMC can check the benchmarks used at the hardware model checking competition 2008. A PERL script is provided to run EBMC on these benchmarks. The PATH variable must include the location where the ebmc binary is located before you run the script.
This research is supported by the Semiconductor Research Corporation (SRC) under contracts no. 2006-TJ-1539 and 2012-TJ-2269.