module bios(cs, addr, CLK, bios_valid, dataout); input cs; input [31:0] addr; input CLK; output bios_valid; output [31:0] dataout; `define BOOT_LENGTH 6 reg [31:0] imemory[0:`BOOT_LENGTH - 1]; reg [31:0] wait_cycles; reg [31:0] address; reg bios_valid; reg [31:0] dataout; initial begin imemory[0] = 32'b0; imemory[1] = 32'b1; imemory[2] = 32'b10; imemory[3] = 32'b11; imemory[4] = 32'b100; imemory[5] = 32'b101; end always @ (posedge CLK) begin if(cs == 1) begin address = addr; if (address < `BOOT_LENGTH) begin repeat(2) @(posedge CLK); dataout = imemory[address]; bios_valid = 1; @(posedge CLK); bios_valid = 0; @(posedge CLK); end else begin bios_valid = 0; @(posedge CLK); end end else begin @(posedge CLK); end end endmodule