module fir_fsm(clock, reset, in_valid, state_out); input clock; input reset; input in_valid; output [31:0] state_out; reg [3:0] state; reg [31:0] state_tmp; reg [31:0] state_out; `define RESET_S 3'b000 `define FIRST_S 3'b001 `define SECOND_S 3'b010 `define THIRD_S 3'b011 `define OUTPUT_S 3'b100 always @(posedge clock) begin if(reset == 1'b1) begin state <= `RESET_S; end else begin case(state) `RESET_S: begin state = `FIRST_S; state_tmp = 0; state_out = state_tmp; end `FIRST_S: begin if(in_valid == 1) begin state = `SECOND_S; end state_tmp = 1; state_out = state_tmp; end `SECOND_S: begin state = `THIRD_S; state_tmp = 2; state_out = state_tmp; end `THIRD_S: begin state = `OUTPUT_S; state_tmp = 3; state_out = state_tmp; end default: begin state = `FIRST_S; state_tmp = 4; state_out = state_tmp; end endcase end end endmodule module fir_data(reset, state_out, sample, result, output_data_ready); input [31:0] state_out; input reset; input [31:0] sample; output [31:0] result; output output_data_ready; wire [8:0] coefs[0:15]; reg [7:0] sample_tmp; reg [18:0] acc; reg [7:0] shift[0:15]; reg [5:0] i; reg [31:0] result; reg output_data_ready; reg [31:0] state; assign coefs[0] = -6; assign coefs[1] = -4; assign coefs[2] = 13; assign coefs[3] = 16; assign coefs[4] = -18; assign coefs[5] = -41; assign coefs[6] = 23; assign coefs[7] = 154; assign coefs[8] = 222; assign coefs[9] = 154; assign coefs[10] = 23; assign coefs[11] = -41; assign coefs[12] = -18; assign coefs[13] = 16; assign coefs[14] = 13; assign coefs[15] = -4; always @(reset or state_out or sample) begin if (reset == 1'b1) begin sample_tmp = 0; acc = 0; for(i = 0; i <= 15; i = i+1) begin shift[i] = 0; end end result = 0; output_data_ready = 0; state = state_out; case (state) 1: begin sample_tmp = sample; acc = sample_tmp*coefs[0]; acc = acc + shift[14]* coefs[15]; acc = acc + shift[13]*coefs[14]; acc = acc + shift[12]*coefs[13]; acc = acc + shift[11]*coefs[12]; end 2: begin acc = acc + shift[10]*coefs[11]; acc = acc + shift[9]*coefs[10]; acc = acc + shift[8]*coefs[9]; acc = acc + shift[7]*coefs[8]; end 3: begin acc = acc + shift[6]*coefs[7]; acc = acc + shift[5]*coefs[6]; acc = acc + shift[4]*coefs[5]; acc = acc + shift[3]*coefs[4]; end 4: begin acc = acc + shift[2]*coefs[3]; acc = acc + shift[1]*coefs[2]; acc = acc + shift[0]*coefs[1]; for(i=14; i>=0; i=i-1) begin shift[i+1] = shift[i]; end shift[0] = sample; result = acc; output_data_ready = 1; end endcase end endmodule module fir(SAMPLE, IN_VALID, RESET, CLK, OUTPUT_DATA_READY, RESULT); input [31:0] SAMPLE; input IN_VALID; input RESET; input CLK; output OUTPUT_DATA_READY; output [31:0] RESULT; wire [31:0] state_out; wire [31:0] result_ins; wire output_data_ready_ins; reg [31:0] RESULT; reg OUTPUT_DATA_READY; fir_fsm fir_fsm1 (.clock(CLK), .reset(RESET), .in_valid(IN_VALID), .state_out(state_out)); fir_data fir_data1 (.reset(RESET), .state_out(state_out), .sample(SAMPLE), .result(result_ins), .output_data_ready(output_data_ready_ins)); always @(posedge CLK) begin RESULT = result_ins; OUTPUT_DATA_READY = output_data_ready_ins; end endmodule